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INTEGRATED CIRCUITS
74F573 Octal transparent latch (3-State) 74F574 Octal transparent latch (3-State)
Product specification IC15 Data Handbook 1989 Oct 16
Philips Semiconductors
Philips Semiconductors
Product specification
Latch/flip-flop
74F573 Octal Transparent Latch (3-State) 74F574 Octal D Flip-Flop (3-State)
FEATURES
74F573/74F574
* 74F573 is broadside pinout version of 74F373 * 74F574 is broadside pinout version of 74F374 * Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
The 74F574 is functionally identical to the 74F374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocesors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. TYPICAL SUPPLY CURRENT (TOTAL) 35mA TYPICAL SUPPLY CURRENT (TOTAL) 50mA
* Useful as an Input or Output port for Microprocessors * 3-State Outputs for Bus interfacing * Common Output Enable * 74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
* 3-State Outputs glitch free during power-up and power-down * These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74F573 is functionally identical to the 74F373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs is transferred to the latch outputs when the Enable (E) input is High. The latch remains transparent to the data input while E is High and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independent to the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
TYPE 74F573
TYPICAL PROPAGATION DELAY 5.0ns
TYPE 74F574
TYPICAL fMAX 180MHz
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL 20-Pin Plastic SSOP COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F573N, N74F574N N74F573D, N74F574D N74F573DB PKG DWG # SOT146-1 SOT163-1 SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D7 E (74F573) OE CP (74F574) Data inputs Latch Enable input (active falling edge) Output Enable input (active Low) Clock Pulse input (active rising edge) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 3.0mA/24mA
Q0 - Q7 3-State outputs NOTE: One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state.
1989 Oct 16
2
853-0083 97897
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
PIN CONFIGURATION - 74F573
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E
PIN CONFIGURATION - 74F574
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP
GND 10
GND 10
SF01073
SF01074
LOGIC SYMBOL - 74F573
2 3 4 5 6 7 8 9
LOGIC SYMBOL - 74F574
3 4 5 6 7 8 9
2
D0 11 E
D1
D2
D3
D4
D5
D6
D7 11 CP
D0
D1
D2
D3
D4
D5
D6
D7
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 VCC=Pin 20 GND=Pin 10
18
17
16
15
14
13
12 VCC=Pin 20 GND=Pin 10
19
18
17
16
15
14
13
12
SF01075
SF01076
LOGIC SYMBOL (IEEE/IEC) - 74F573
1 11 EN1 EN2 19 18 17 16 15 14 13 12
LOGIC SYMBOL (IEEE/IEC) - 74F574
1 11 EN1 C2 19 18 17 16 15 14 13 12
2 3 4 5 6 7 8 9
2D
1
2 3 4 5 6 7 8 9
2D
1
SF01077
SF01078
1989 Oct 16
3
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
LOGIC DIAGRAM - 74F573
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D E Q
D E Q
D E Q
D E Q
D E Q
D E Q
D E Q
D E Q
E
11
OE
1 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
VCC=Pin 20 GND=Pin 10
Q0
SF01079
FUNCTION TABLE - 74F573
INPUTS OE L L L L L H H H= h= L= l= NC= X= Z= = E H H L L H Dn L H l h X X Dn INTERNAL REGISTER L H L H NC NC Dn OUTPUTS Q0 - Q7 L H L H NC Z Z OPERATING MODES Load and read register Latch and read register Hold Disable outputs
High voltage level High voltage level one setup time prior to the High-to-Low E transition Low voltage level Low voltage level one setup time prior to the High-to-Low E transition No change Don't care High impedance "off" state High-to-Low E transition
LOGIC DIAGRAM - 74F574
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
CP
11
OE
1 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
VCC=Pin 20 GND=Pin 10
Q0
SF01080
1989 Oct 16
4
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
FUNCTION TABLE - 74F574
INPUTS OE L L L H= h= L= l= NC= X= Z= = = CP Dn l h X INTERNAL REGISTER L H NC OUTPUTS Q0 - Q7 L H NC Z OPERATING MODES Load and read register Hold Disable outputs
H Dn Dn High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5.0 -0.5 to +VCC 48 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -3 24 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C
1989 Oct 16
5
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG 10%VCC 5%VCC 10%VCC 5%VCC MIN 2.4 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 50 -50 -60 30 74F573 VCC = MAX 35 40 45 74F574 VCC = MAX 50 -150 40 50 60 65 70 TYP
NO TAG
MAX
UNIT V V V V V A A mA A A mA mA mA mA mA mA
VO OH
High-level High level output voltage
VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX
VO OL VIK II IIH IIL IOZH IOZL IOS
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, High-level voltage applied Off-state output current, Low-level voltage applied Short-circuit output currentNO TAG ICCH ICCL Supply current (total) ( )
ICC
ICCZ ICCH ICCL
ICCZ 55 85 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1989 Oct 16
6
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPZH tPZL Propagation delay Dn to Qn Propagation delay E to Qn Output Enable time to High or Low level 74F573 Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG 74F574 Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG 3.0 1.0 4.5 3.0 2.5 2.5 TYP 5.5 3.5 8.5 5.0 5.5 5.5 MAX 8.0 6.0 11.5 7.0 9.5 8.0 Tamb = 0C to +70C VCC = +5V 10% CL = 50pF, RL = 500 MIN 2.5 1.0 4.0 2.5 2.0 2.0 MAX 9.0 7.0 12.5 8.0 10.5 8.5 ns ns UNIT
ns
tPHZ tPLZ fMAX tPLH tPHL tPZH tPZL
Output Disable time from High or Low level
1.0 1.0
3.0 2.5
6.0 5.5
1.0 1.0
6.5 5.5
ns
Maximum Clock frequency Propagation delay CP to Qn Output Enable time to High or Low level
160 3.5 3.5 2.5 3.0
180 5.0 5.0 4.5 5.0 7.5 7.5 7.5 8.0
150 3.0 3.0 2.0 3.0 8.0 8.0 7.5 8.5
MHz ns
ns
tPHZ tPLZ
Output Disable time from High or Low level
1.0 1.0
3.0 2.5
5.5 5.5
1.0 1.0
6.0 6.0
ns
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) tw(H) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, Dn to E Hold time, Dn to E E pulse width, High Setup time, Dn to CP Hold time, Dn to CP CP Pulse width, High or Low 74F574 74F573 Waveform 4 Waveform 4 Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG 0.0 1.5 2.5 4.0 3.0 2.5 2.5 0 0 3.0 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 0.0 2.0 2.5 4.0 3.5 3.0 3.0 0 0 3.0 4.0 MAX ns ns ns ns ns ns UNIT
1989 Oct 16
7
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
AC WAVEFORMS
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX Dn VM tPLH tPLH Qn Qn VM VM VM VM VM tPHL
E, CP
VM tW(H) tPHL
VM tW(L)
VM
SF01081
SF01082
Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock Frequency
Waveform 2. Propagation Delay for Data to Outputs
Dn
VM ts(H)
VM th(H)
VM ts(L)
VM th(L)
Dn
VM ts(H)
VM th(H)
VM ts(L)
VM th(L)
CP
VM
VM
E
VM
VM
SF00191
SF00992
Waveform 3. Data Setup and Hold Times
Waveform 4. Data Setup and Hold Times
OE
VM tPZH
VM tPHZ VM 0V VOH -0.3V
OE
VM tPZL
VM tPLZ VM VOL +0.3V
Qn
Qn
SF00343
SF00344
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
1989 Oct 16
8
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1989 Oct 16
9
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1989 Oct 16
10
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1989 Oct 16
11
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1989 Oct 16
12
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
NOTES
1989 Oct 16
13
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05141
Philips Semiconductors
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